FIGS. 5(a) to 5(d) illustrate process steps in a prior art method for producing a semiconductor device. In FIG. 5, reference numeral 1 designates a semi-insulating GaAs substrate. An active layer 2 is produced in the GaAs substrate 1. A refractory metal 4 is disposed on the active layer 2. A gate electrode 4' is made of the refractory metal 4. An n.sup.+ type diffusion layer 5 is disposed at both sides of the gate electrode 4'. A source electrode 6 and a drain electrode 7 are disposed on the n.sup.+ type diffusion layer 5. Reference numeral 11 designates a photoresist.
The production process will be described.
First of all, as shown in FIG. 5(a), an active layer 2 is produced at a desired position in a semi-insulating GaAs substrate 1 by ion implantation.
Next, as shown in FIG. 5(b), a refractory metal 4, such as tungsten silicide (hereinafter referred to as WSi.sub.x) is deposited on the entire surface of the semi-insulating GaAs substrate 1 by sputtering or vapor deposition, and a pattern of photoresist 11 is formed where a gate is to be prepared.
Next, as shown in FIG. 5(c), the WSi.sub.x 4 is removed by reactive ion etching using the photoresist 11 as a mask, thereby producing a gate electrode 4'.
Next, as shown in FIG. 5(d), ion implantation, using the WSi.sub.x 4' as a mask, produces a high dopant concentration regions 5 (hereinafter referred to as n.sup.+ layer) after annealing, and a drain electrode 6 and a source electrode 7 are respectively produced thereon.
In the prior art production method of a semiconductor device, in order to produce a gate electrode 4', patterning of the photoresist 11 is required, and the precision of pattern gate depends on the precision of the photolithographic alignment technique. Furthermore, because ion implantation uses the WSi.sub.x 4' as a mask, the n.sup.+ layers 5 below the source electrode 7 and the gate electrode 4' are located close to each other, and, thus, the source resistance is lowered. This is advantageous for the gain of the FET. However, since the n.sup.+ layers below the drain electrode 6 and the gate electrode 4' are close to each other, the gate-drain breakdown voltage is reduced. This makes it difficult to apply this structure to high power analog ICs.